The forecasts for internet data volume growth in the next few years are massive. This growth is strongly driving all the IC technology which touch and handles and utilizes this data. In a similar fashion the needs are going to push the for new IC testing solutions and capabilities. This presentation will explore the various IC along this data-path and pinpoint the changing test requirements which are driving the industry and Advantest moving forward. This discussion will start by exploring the test challenges associate with the various sensors, human interfaces and smart phones, and then follow the data-path up the ladder to the cloud-based solutions where signal routing and artificially intelligent tools are demanding high-speed, high-power, and very creative new test solutions.
Director of Business Development
To Deliver on the Promise of AI: Find a Trusted Test Partner
AI has sparked a new generation of chip development that touches many of the devices and applications we use daily: cloud infrastructure, automotive, smart home and edge devices. These devices are driving more data, computing power, and advanced algorithms, and as they become more complex, test strategies must also evolve. Join Teradyne in this open discussion as we address AI devices in areas such as scan, high power, and high speed, and learn more about the AI partnership Teradyne provides.
Business Development Manager, Global Account Manager, Technical Manager
ZUBIR EBRAHIM, ROBIN YUEN, KEVIN KIM
ISE Test Development Services
ISE Labs engineering offers full test program development, and test consulting services.
This presentation describes how our engineering team can increase fault coverage and improve productivity of device debug and bring-up. This includes pattern conversions from customer design teams, support for protocol aware programming, and intelligent register dumps for device debug from any test program location.
Our analysis tools can characterize test program robustness and assist with setting the test limits. We created a fictional device, the ISE926, with test data based on arbitrary values. We added in gaussian noise and location-based dependencies, to illustrate our methods. We will show statistical plots, 3-D wafer maps and contour maps, data converter analysis, gage R&R (repeatability and reproducibility), CPK analysis, and identification of good die in bad neighborhoods.
A discussion of our primary tester platforms, and a technology roadmap will be provided.
Product Development Test Engineering Manager
Driving Cost Down for ESD/EOS Testing
Discussion on techniques to reduce ESD test cycle cost using wafer/die level testing techniques to verify ESD and EOS robustness before going to package.
Senior Staff Scientist
Considerations for HTOL Stress Testing of Ultra High Power Integrated Circuits
The topic of the talk is HTOL testing for high-power ICs. Our industry has seen a loss of reliability lifetime margin over the past several Si technology nodes. This loss of margin raises concern particularly for high-power designs that have an expectation of 10-year lifetime. Further there are new transistor aging instabilities to be aware of with FinFET devices, that should be accounted for in an HTOL test plan, for that testing to be sufficient to demonstrate circuit stability over time. The talk addresses considerations for HTOL stress testing for ultra high-power ICs, as well as the new and critical role for ongoing reliability monitoring in production, in light of reliability margin erosion and new aging instabilities. An existing commercially available HTOL system solution for UHP ICs is offered.